The invention relates to an output driver circuit having a driver device, which is connected to a signal input and to a signal output. The invention also relates to a method for adjusting such a driver device.
Output drivers, which are also referred to as off-chip drivers, are a major component of large-scale integrated semi-conductor circuits, particularly DRAMs. The output drivers are used to produce defined voltage signals, which can then be interpreted as binary signals. Furthermore, output drivers may also be used to initiate specific processes in downstream electronic assemblies with the aid of the generated voltage signal.
As a result of increasing clock rates, in particular in the case of DRAMs as well, there is a need for the output time of data to be maintained as exactly as possible. For the output driver, this means that its output generates an output signal at a defined signal amplitude at a predetermined time which (for example, as in the case of synchronous DRAMs) can be coupled to the clock system for synchronization.
One characteristic variable for the synchronicity of the output time of the driver output signal is the time difference between a change in a data item at the output and the clock signal, which predetermines the output time for the change in the data item. The time difference is generally specified as the time interval between the time at which the clock signal crosses half its maximum amplitude and the time at which the output signal from the output driver reaches a predetermined reference voltage.
In the ideal case, the time interval is zero, which means that the output signal from the output driver is synchronized to the clock signal. The optimum operating point is annotated by reference symbol B in FIG. 1. FIG. 1 shows a voltage signal output from an output driver for a synchronous DRAM, in which the signal output is coupled to the system clock. The clock signal is an ideal square-wave signal with a period of 10 ns with a maximum voltage amplitude of 1.8 V. The output signal from the output driver likewise has an essential square waveform with short rise and fall times, that is steep flanks or edges, with the voltage magnitude being 1.6 V, and the signal offset being 0.2 V. A voltage level of 0.9 V is specified as the reference voltage.
The output signal is then interpreted by the downstream assemblies as a logic 1, when it is above the reference voltage, and is interpreted as a logic 0 when it is below the reference voltage.
At the operating point A, FIG. 1 shows the situation in which the output voltage crosses the reference voltage at a time interval xcex94t1 before the time at which the clock signal reaches half its maximum voltage. The change in the data item thus takes place before the clock signal, so that the clock signal and the signal output are not exactly synchronous. The operating point C shows the situation in which the change in the data item, i.e., the time at which the output voltage crosses the reference voltage, lags by the time interval xcex94t2 behind the time at which the time signal corresponds to half the maximum voltage. The output signal from the output driver is not synchronized exactly to the clock signal in this situation either.
In synchronous DRAMs, the time difference between the change in the data item and the clock signal, as shown at the operating point B, should ideally be zero, but, depending on the use of the synchronous DRAM, may also lie within the specified time window, with a maximum specified error of, for example, 750 ps.
A major problem in this case is that the output drivers are subject to production process fluctuations, which influence the desired synchronicity between the output signal from the output driver and the clock signal for the synchronous DRAM. The output time from the output driver circuit furthermore depends, to a major extent, on the operating voltage, on the ambient temperature and, above all, on the load that is connected. An auxiliary circuit is therefore frequently provided for synchronous DRAMs in order to simulate the output driver to make it possible to predict any change in the output time as a result of a change in the operating conditions. The influence of the load (i.e., the downstream electronic component) on the output time cannot, however, be taken into account by such an auxiliary circuit.
It is accordingly an object of the invention to provide an output driver circuit and a method for adjustment of a driver device that overcome the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type, and that allow the output time of the signals from the output driver to be set exactly, independently of the operating conditions.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a delay device between a signal input and a driver circuit in an output driver circuit, which allows the input signal to the driver device to be delayed by a predetermined value. The signal amplitude of the output signal from the driver device is compared in a comparison device with the signal amplitude of a reference signal at a predetermined time, and the time delay for the input signal to the driver device is then set on the basis of the comparison result.
The output driver circuit and the associated method allow the time at which the input signal is applied to the driver circuit, and hence the time at which the output signal is generated by the driver circuit to be adjusted exactly by adjusting the signal delay value from the delay device that is connected upstream of the driver circuit. The adjusting method is carried out by evaluating the output signal from the driver circuit for a predetermined delay at a predetermined evaluation time. A determination is made at the evaluation time if the output signal has reached a desired reference level, and the delay in the input signal to the driver circuit is then adjusted on the basis of this comparison result. The procedure according to the invention allows the output time for the output signal from the driver circuit to be set exactly independently of the respective operating conditions (that is, independently of the ambient temperature, of the applied operating voltage and, above all, also of the connected load).
In accordance with another feature of the invention, the comparison device is triggered at a predetermined clock rate, in order to repeatedly compare the signal amplitude of the output signal from the driver device with the signal amplitude of the reference signal. The time delay for the input signal to the driver device is lengthened by a predetermined value when the comparison result shows that the signal amplitude of the output signal from the driver device is less than the signal amplitude of the reference signal. However, when the comparison result shows that the signal amplitude of the output signal from the driver device is greater than the signal amplitude of the reference signal, the time delay for the input signal to the driver device is shortened by a predetermined value. This makes it possible to set the output time of the output signal from the output driver circuit to the desired value in a self-adjusting manner, with the delay being matched to the ideal value step-by-step.
In accordance with a further feature of the invention, when the error in the comparison of the signal amplitudes of the output signal and of the reference signal is within a predetermined range, the operating point for the time delay for the input signal and hence the output time of the output signal from the driver circuit are fixed. Alternatively, it is also possible not to fix the operating point, and to allow the time delay, and hence the output time of the output signal of the driver circuit, to oscillate with small errors about the optimum.
With the objects of the invention in view, there is also provided a method of adjusting a driver device connected to a signal input and to a signal output for generating a predetermined output signal in response to an applied input signal, which includes the steps of comparing a signal amplitude of the output signal of the driver device with another signal amplitude of a reference signal at a predetermined time, setting a value for delaying the input signal to the driver device based on a result of the comparing step, and delaying the input signal to the driver device by the given value.
In accordance with a concomitant mode of the invention, the method also includes the steps of repeating the comparison of the signal amplitude of the output signal of the driver device with the signal amplitude of the reference signal at a predetermined clock rate, lengthening the time delay of the input signal to the driver device by a predetermined value when the signal amplitude of the output signal of the driver device is less than the signal amplitude of the reference signal, and shortening the time delay of the input signal to the driver circuit by the predetermined value when the signal amplitude of the output signal of the driver device is greater than the signal amplitude of the reference signal.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an output driver circuit and a method for adjustment of a driver device, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.